Researchers at IIITD are working at the intersection of compression and hardware acceleration of Deep Learning models. The goal is to develop AI/ML solutions that can perform equally well on the edge, where the availability of resources like power, computation and memory is substantially limited. This research introduces a novel Symmetric k-means based compression algorithm that is specifically designed to support a new FPGA-based hardware acceleration scheme by reducing the number of inference-time multiply-accumulate (MAC) operations by up to 98%. As opposed to popular quantization based model compression schemes that are typically evaluated on classification tasks, this approach works well for regression tasks as well. The approach is evaluated for different computer vision tasks like image classification, object detection and depth estimation over different Convolutional Neural Network architectures.

This work has recently been accepted as a Special Issue paper in the IEEE Journal of Selected Topics in Signal Processing  (IF=6.688) with the title “Symmetric k-means for Deep Neural Network Compression and Hardware Acceleration on FPGAs”. The team responsible for this accomplishment comprises of Akshay Jain (PhD scholar, IIITD), Pulkit Goel (B.Tech. ECE graduate, IIITD), Shivam Aggarwal (B.Tech. ECE 4th year, IIITD), Dr. Alexander Fell (Adjunct Faculty, IIITD) and Dr. Saket Anand (Faculty, IIITD). This work was partially supported by Infosys Center for Artificial Intelligence at IIIT-Delhi and Microsoft Research, India.